A block diagram of the converter together with a classical reconstruction scheme is illustrated in Figure 5. The classical way to reconstruct the discretized analog signal is by low-pass filtering, with σ∕2π cutoff frequency, a pulse train which is modulated by the quantized sequence of samples. Oversampled A/D conversion as a process of digital encoding of analog signals involves discretization of a σ-bandlimited analog signal in time, implemented as sampling with a time interval τ, followed by discretization in amplitude, that is quantization of the sequence of samples with a quantization step q. It can deliver an 8-bit output in 3.3 nanoseconds. The AD9028 high-speed 8-bit A/D converter circuit, manufactured by Analog Devices, Inc., is an example of a parallel converter. The complexity, however, is less than that of a pure parallel converter circuit. This multistage method of parallel A/D conversion is faster than nonparallel methods but slower than a pure parallel approach. The difference voltage is then converted with a second parallel converter to produce the least significant bits of the digital result. This converter generates the most significant bits in the converted number, and the digits are then reconverted to analog with a D/A converter and subtracted from the original input signal. This hybrid method essentially consists of applying the analog voltage to a small (4–7 bits) parallel converter. It is also possible to utilize the parallel converter in a hybrid configuration that gains some of the advantage of parallel conversion and yet avoids the geometrically increasing complexity normally associated with it. Actual converter circuits, however, may use any one of a variety of codes, including binary, Gray Code, excess-3, and others. The converted digital output for the given converter is in standard binary format. The chapter concludes with a small discussion on further nonidealities of ΔΣ modulators, which are largely outside the scope of this text. The pros and cons for using a MASH converter versus a single-loop converter are given. Next, the signal processing of the MASH architecture, which is comprised of a cascade of basic ΔΣ modulators, is studied. The architectures of continuous-time and discrete-time ΔΣ modulators are presented, and the advantages and disadvantages of each design architecture are given in some detail.
The concept of oversampled converters and ΔΣ modulation and the basic loop dynamics are derived. We also discuss the impact of key performance parameters such as dynamic range, harmonic distortion, and thermal noise on the performance of the converter. We also introduce the Nyquist converters and delve into the architectural details of the FLASH, pipelined, and folding ADC architectures. Topics such as aperture time accuracy, clock feedthrough, and charge injection and their impact on the signal-to-noise ratio (SNR) are also discussed. We discuss the main building blocks of ADCs, namely track-and-hold amplifiers and comparators. In this chapter, we discuss the various hardware architectures in which an analog-to-digital converter (ADC) can be implemented. This process could take place at baseband, as is the case of direct conversion receivers, or at intermediate frequency (IF) or low IF depending on the requirements and consequently on the receiver architecture pursued by the designers. Rouphael, in Wireless Receiver Architectures and Design, 2014 AbstractĪnalog to digital conversion is the process of transforming the signal from the analog domain to the digital domain.
0 kommentar(er)
